Field of the Disclosure
Aspects of the present disclosure generally relate to data storage systems, and more particularly, to techniques for fabricating magnetic random access memory (MRAM) bits on a tight pitch.
Description of the Related Art
Higher storage bit densities in magnetic media used in disk drives have reduced the size (volume) of magnetic bits. Magnetic random access memory (MRAM) offers fast access time, infinite read/write endurance, radiation hardness, and high storage density. Unlike conventional RAM chip technologies, MRAM data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The elements are formed from two magnetically polarized plates, each of which can maintain a magnetic polarization field, separated by a thin insulating layer, which together form a magnetic tunnel junction (MTJ) layer. MRAM cells including MTJ memory elements can be designed for in-plane or perpendicular magnetization of the MTJ layer structure with respect to the film surface. One of the two plates is a permanent magnet (i.e., has fixed magnetization) set to a particular polarity; the polarization of the other plate will change (i.e., has free magnetization) to match that of a sufficiently strong external field. Therefore, the cells have two stable states that allow the cells to serve as non-volatile memory elements.
A memory device may be built from a grid of such cells. The MRAM cells in an array on a chip are connected by metal word and bit lines. Each memory cell is connected to a word line and a bit line. The word lines connect rows of cells, and bit lines connect columns of cells. Typically complementary metal-oxide semiconductor (CMOS) structures include a selection transistor which is electrically connected to the MTJ stack through the top or bottom metal contacts. The direction of the current flow is between top or bottom metal electrodes.
Reading the polarization state of an MRAM cell is accomplished by measuring the electrical resistance of the cell's MTJ. A particular cell is conventionally selected by powering an associated transistor that switches current from a supply line through the MTJ layer to a ground. Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the relative orientation of the polarizations in the two magnetic layers of the MTJ. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the polarity of the free writable (free) layer determined. If the two layers have the same polarization, this is considered to mean State “0”, and the resistance is “low,” While if the two layers are of opposite polarization the resistance will be higher and this means State “1”. Data is written to the cells using a variety of techniques. In conventional MRAM, an external magnetic field is provided by current in a wire in proximity to the cell, which is strong enough to align the free layer. Spin-transfer-torque (STT) MRAM uses spin-aligned (“polarized”) electrons to directly torque the domains of the free layer. Such polarized electrons flowing into the free layer exert a sufficient torque to realign (e.g., reverse) the magnetization of the free layer.
Ion Beam Etching (IBE) (i.e., ion milling) has been widely used in various industries for patterning thin films. Etching and re-deposition may occur simultaneously. When the deposition rate is larger than the etching rate, redeposition material accumulates on the sidewall. When the etching rate is higher, the sidewall is cleaned up. Shallow slope is helpful for preventing the re-deposition. The higher or more vertical the slope, the more susceptible it is to re-deposition since the lateral component of etch rate in directional etching ambient such as IBE is, in general, less than the vertical component. When a conductive material is re-deposited on the MTJ sidewall at the barrier layer, the top and bottom magnetic layers are shorted.
One significant determinant of a memory system's cost is the density of the components. Smaller components, and fewer components for each cell, enable more cells to be packed onto a single chip, which in turn means more chips can be produced at once from a single semiconductor wafer and fabricated at lower cost and improved yield. At large pitch (e.g., 5F), MRAM bits may be formed with little to no re-deposition on the sidewall as shown in FIG. 1 but with a lower density of bits. At tight pitch (e.g., 2F), MRAM bits may be formed with a higher density; however, re-deposition of etched material on the sidewall is a serious concern, because it can make it the device inoperable by forming an electrical short across the barrier layer, for example, as shown in FIG. 2.
Therefore, a need exists in the art for MRAM bit fabrication at tight pitch.